An Integrated Program Representation for Loop Optimizations

Title of thesis: AN INTEGRATED PROGRAM REPRESENTATION FOR LOOP OPTIMIZATIONS Greeshma Yellareddy, Master of Science, 2011 Thesis directed by: Professor Rajeev Barua Department of Electrical and Computer Engineering Inspite of all the advances, automatic parallelization has not entered the general purpose compiling environment for several reasons. • There have been two distinct schools of thought in parallelization domain namely, affine and non-affine which have remained incompatible with each other over the years. Thus, a good practical compiler will have to be able to analyze and parallelize any type of code – affine or non-affine or a mix of both. • To be able to achieve the best performance, compilers will have to derive the order of transformations best suitable for a given program on a given system. This problem, known as “Phase Ordering”, is a very crucial impedance for practical compilers, more so for parallelizing compilers. The ideal compiler should be able to consider various orders of transformations and reason about the performance benefits of the same. In order to achieve such a compiler, in this paper, we propose a unified program representation which has the following characteristics: • Modular in nature. • Ability to represent both affine and non-affine transformations. • Ability to use detailed static run-time estimators directly on the representation. AN INTEGRATED PROGRAM REPRESENTATION FOR LOOP OPTIMIZATIONS